The present invention relates to the fabrication of integrated circuit devices and, in particular, to a selective plasma etch process using a time modulated DC bias to simultaneously control deposition and etching for different portions and/or aspect ratios of the integrated circuit device.
Etch techniques are widely used during the fabrication of semiconductor devices for integrated circuits. Chemical etching in liquid or gaseous form, for example, is used to remove a material not protected by hardened photoresist material. A particularly effective etching technique is plasma etching. Plasma is a collection of electrically charged and neutral particles.
In a plasma, the density of negatively-charged particles (electrons and negative ions) is generally equal to the density of positively-charged particles (positive ions). Plasma generation may be conducted by applying power to electrodes in a chamber of a reactor. In diode or parallel plate reactors, power is applied to one electrode to generate a plasma. In triode reactors, power is typically applied to two of three electrodes to generate a plasma.
In radio frequency (RF) plasma generation, for a diode reactor, a sinusoidal signal is sent to an electrode or a pair of electrodes. Conventionally, a chuck or susceptor is the powered electrode. Examples of parallel plate reactors include the 5000MERIE from Applied Materials, Santa Clara, Calif.
A plasma source material, typically includes one or more gases, such as, for example, argon, silane (SiH4), oxygen, TEOS, diethylsilane, silicon tetrafluoride (SiF4) and fluorocarbon gases, directed to an interelectrode gap between the pair of electrodes. The amplitude of the RF signal must be sufficiently high for a breakdown of plasma source material. In this manner, electrons have sufficient energy to ionize the plasma source material and to replenish the supply of electrons to sustain a plasma. The ionization potential, the minimum energy needed to remove an electron from an atom or molecule, varies with different atoms or molecules.
In a typical triode reactor, three parallel plates or electrodes are used. The middle or intermediate electrode is conventionally located in between a top and bottom electrode, and thus two interelectrode cavities or regions are defined (one between top and middle electrode and one between middle and bottom electrode). The middle electrode typically has holes in it. Conventionally, both the top and bottom electrode are powered via RF sources, and the middle electrode is grounded. Examples of triode reactors are available from Lam Research, Fremont, California, and Tegal Corporation Ltd., San Diego, Calif.
Parallel plate and triode reactors generate capacitively coupled plasmas. These are conventionally xe2x80x9clow densityxe2x80x9d plasmas (ion-electron density of less than or equal to 1010 ions-electrons per cm3) as compared with high-density plasmas (ion-electron density on the order of about 1011 to about 1013 ions-electrons per cm3) which are generated by systems such as, electron cyclotron resonance (ECR), inductively coupled plasma (ICP), microwave and other high frequency source plasmas. For ICP systems, an inductive coil (electrode) is conventionally driven at a high frequency using an RF supply. The inductive coil and RF supply provide a source power, or top power, for plasma generation. In ECR systems, a microwave power source (for example, a magnetron) is used to provide a top power. All of these systems, including ICP and ECR systems, have a separate power supply known as bias power or bottom power, which may be employed for directing and accelerating ions from the plasma to a substrate assembly or other target. In either case, voltage that forms on a susceptor or chuck (also known as the direct current (DC) bias), is affected by the bottom power (RF bias); whereas, current is affected by the top power.
Plasma may also be used to deposit films over a substrate. In a plasma enhanced CVD (PECVD) process, high electron temperatures are employed to increase the density of disassociated species within the plasma. These disassociated species or radicals are available for deposition on a substrate assembly surface. The high-density plasma may be employed to facilitate deposition. A high density plasma is typically defined as having an ion-electron density on the order of 1011 to 1013 ions-electrons per cm3. Additionally, in a pulsed-PECVD process a pulsed-plasma is provided by turning the bias power xe2x80x9conxe2x80x9d and xe2x80x9coffxe2x80x9d.
As noted, plasma apparatus have been used to either deposit or remove material from an integrated circuit device, for example, a wafer containing many die.
In designing a plasma etching or deposition process, it is desirable to have a large process window with a sensitivity as small as possible, so that large discrepancies in equipment performance can be tolerated. As the film thickness and device dimensions decrease, etch selectivity and uniformity become increasingly significant. Selectivity is the ability to etch one layer faster than another layer under the same etching conditions whereas uniformity refers to the ability of the process to evenly remove the desired layer.
In prior methods, plasma etch/or deposition selectivity has been controlled by various methods, including varying the gas phase chemistry through adjustments in the plasma reactor gases, adjusting the operating pressure, adding diluent gases, or increasing the pumping speed to allow high flow at low pressure operation.
Etch selectivity is of particular interest when, for example, a device requires selective removal of different layers to obtain desired shapes and dimensions in various parts of the same device. Apart from selectivity, etching rates and profiles depend on feature size and pattern density. Problems in achieving microscopic uniformity arise often as most high performance etches are aspect ratio-dependent etches (ARDE). In ARDE etches, the rate of oxide removal is dependent upon the aspect ratio of the opening, which is defined as the ratio of the depth of the opening to the diameter. As such, features with a high aspect ratio etch more slowly than trenches with a small aspect ratio. In other words, the oxide etch rate, in terms of linear depth etched per unit time, is smaller for high aspect ratio openings than for low aspect ratio openings. Thus, the etching rate decreases as the feature dimensions are reduced. Alternatively, the features are etched such that they do not have a uniform cross section along the length of the feature.
Advanced technologies require high etch performance in high aspect ratio features, and demand high etch performance in layers having features at different aspect ratios. Several attempts have been made to overcome the aspect ratio-dependency effects and the above-described difficulties in the etching process. However, the prior methods have small process windows which are difficult and expensive to sustain in manufacturing. Some of the methods also require extensive redesign of the process or devices, and use of unproven and costly equipment. Accordingly, there is a need for an improved etch selectivity, with an improved process window, which has the ability to operate under a wide range of aspect ratios.
The present invention relates to a method for improving the process window for etch processes, such as for example, a Self-Aligned Contact (SAC) etch using a time modulated DC bias in a plasma etching apparatus. The present invention pulses the bias power to tailor and modulate a deposition vs. removal ratio of similar materials having different aspect ratios to obtain better control over the plasma process and the ability to better etch certain features, such as self-aligned contacts.
Since both etch rate and deposition are dependent upon the aspect ratio of the area in which a material is to be removed or deposited, the present invention exploits the relationship between etch rate/deposition rate and aspect ratio and DC bias. Deposition rates of material are generally lower at higher aspect ratios, and the overall deposition rate increases as the DC bias voltage decreases. Etch rates of materials generally increase as DC bias voltage increases. There is a DC bias voltage (VDC) range below which deposition occurs over a wide range of aspect ratios and above which etching occurs under a wide range of aspect ratios. The present invention provides an etching process in which the DC bias voltage is manipulated so that the etch rate can be controlled under etch processes that require both selectivity in a relatively low aspect ratio part of a wafer and the ability to etch higher aspect ratio features into the same feature, or other features, on the same wafer.
The method of the present invention uses a time modulated bias voltage to control the transition from etch to deposition stages for devices with different aspect ratios. For example, a protective layer of material may be deposited on a first position on a semiconductor wafer while a simultaneous etching process takes place at a second position, on the same wafer. Low bias conditions allow the deposition on the first position. High bias conditions further permit the etch front to move towards completion at the second position, without the removal of the features under the protective layer which is deposited at the first position.
The use of time modulated bias power in etching techniques permits features such as SAC to be defined among materials with similar etch properties, such as thermal oxides and BPSG. In addition, time modulated bias voltage may be used in semiconductor integrated circuits using materials with different etch properties, such as silicon nitride and silicon oxide. In such cases, the process window is expected to be greatly improved.
In addition, the ability to tailor the amount of deposit of each aspect ratio in relation to the amount of etch, which is less sensitive to aspect ratio, permits process optimization over a wide range of designs and features. Moreover, the present invention will improve the capability to precisely control etching in applications that use different aspect ratio features and which must stop on thin etch stop layers. Additional advantages of the present invention will be apparent from the detailed description and drawings, which illustrate preferred embodiments of the invention.